Multiplying and dividing means for electronic calculators



2,834,543 MULTIPLYINC AND DIVIDINC MEANs'FoR ELECTRONIC CALCULATORS Filed July 12, 1952 May 13, 1958 w. H. BURKHART 1o sheets-sheet 1 .W/LL/AM H. BUR/(HART 5%( MW AGE/v7' May 13, 1958 W. H. BURKHART MULTIPLYING AND DIVIDING MEANS FOR ELECTRONIC CALCULATORS Filed July l2, 1952 10 Sheets-Sheet 2 2 6 226 226 2/2 f /96 (/98 222 2M A005 U L L PB s sngcrok 0 /35 D40 l W 232 /23 l" ("0 MSR 7 CONTROL 2/2 f2/3 2/6 26 22a .3257 355 ,mm o/ 0/35 040 04 9 NUMBER: l RECORDS cour/m D92 's 2 al@ E MPC v VVENTOR FIG. 3

W/LL/AM H. BUR/(HART May 13, 1958 l w. H. BLJRKHART '2,834,543

MULTIPLYING AND DIVIDING MEANS FOR ELCTRONIC CALCULATORS Filed July 12, 1952 1o sheets-sheet s 8 (1b /4 tuows gg) 326 32%/` a /99 #Mg/4o 'if' 2H tls-12H8 D @man 2/3 2/6 228 fZOO 2/2 /5 f 226 @25 sus. #DI D/.35 D40 `D4 -1 300 Y 'MVS Afl/usen: -v

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f Y /70 J .vnf-conos Y f2?! /2/ 320 27,0 sp 344 ol MSPP z a/a E c P E Qc MPC FIG 4 E E "26 V QSC /NVENTOR WILL/AM H. BUR/(HART AGENT May 1.3, 1958 w. H. BURKHART '2,834,543

MULTIPLYING AND DIVIDING MEANS FOR ELECTRONIC CALCULATORS 1o sheets-sheet 4 v Filed July 12, 1952 TIME PER/0D COUNTER FIG.

Nl/w rop WILL IAM H. BUR/(HART AGENT- May 13, 1958 w. H. BURKHART MULTIPLYING AND DIVIDING MEANS FOR ELECTRONIC CALCULATORS Filed July l2, 1952 10 Sheets-Sheet 5 FIG.'7

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/NVENTOR A W/LL/AM H. BUR/(HART BVMW Mw AGENT May 13, 1958 w. H. BURKHART 2,834,543

MULTIPLYINC AND DIVIDINC MEANS EOR ELECTRONIC CALCULATORS Filed July 12, 1952 1o sheets-sheet e /Nv/v oR WILL/AM H BUR/(HART A AGENT May 13, 1958 w. H. BURKHART MULTIPLYING AND DIVIDING MEANS FOR ELECTRONIC CALCULATORS 10 Sheets-Sheet '7 Filed July 12, 1952 AGENT 6 Qld Ol May 13, 1958 w. H. BURKHART 2,834,543

NULTIPLYINC AND DIVIDINC MEANs FoR ELECTRONIC CALCULATORS Filed July 12, 1952 10 Shets-Sheet 8 FIG.11

BMW/4%@ May 13, 1958 w. H. BURKHART MULTIPLYINC AND DIVIDINC MEANS ECE ELECTRONIC CALCULATORS 10 Sheets-Sheet 9 Filed July l2, 1952 MNMMMQQQ Y /NVE/VTOR w/L /AM H. BUR/HART May 13, 1958 w. H. BURKHART MULTIPLYING AND DIVIDING MEANS FOR ELECTRONIC CALCULATORS 10 Sheets-Sheet 10 Filed July l2, 1952 NNNNNNNNNNNNNNNNNNNN "NNNNNNNNNNNNNNNNNNNN 4. NNNNNNNNNNNNNNNNNNNN ENTOR w/L/AM H. Bumm/ART 8% M AGENT United States Patent() MULTIPLYING AND DIVIDING MEANS FOR ELECTRNIC CALCULATORS Application July 12, 1952, Serial No. 298,526

36 Claims. (Cl. 23S-6l) This invention relates to new and useful improvements in electronic digital computers and more particularly to means for performing multiplication and division in said computers.

Many method-s of performing multiplication and division are known. Among them is the so-called nine multiples comparison method wherein the irst step is to form the nine multiples of the multiplicand or divisor. In multiplication the next step is to select the multiple appropriate to the highest or lowest order multiplier digit, whichever is more convenient. Then, while the multiple appropriate to the next lower (or higher) order multiplier digit is 4being selected, the rst selected multiple is shifted one digit space relative to the position which the second multiple assumes. The two multiples then are added and their sum is shifted one digit space while the third multiple is being selected, etc. When the multiple appropriate to the last (highest or lowest order) multiplier digit 'has been added to the shifted sum of previous multiples, the resultant sum is the product and the multiplication is completed.

In division the several multiples are compared with the dividend to determine which is the largest multiple divisible into the latter, the said largest one is subtracted from the dividend to form a remainder, the remainder is shifted one space to, in effect, obtain a multiplication by ten, and the remainder is compared with the nine multiples of the divisor, etc.

The principal object of the invention is the provision i in an electronic computer of means for performing multiplication and division in accordance with the above recited methods. Another object of the invention is to construct and arrange the said means in such manner ythat multiplication and division are performed each ina minimum number `of cycles of the computer and in such manner that a maximum num-ber of elements of said means are utilized in fboth operations.

In one embodiment of the invention the means thereof are applied to a cyclically operable serial computer wherein numbers are represented lby electric signal pulses of opposite polarity to represent binary `one and binary zero,

and include 'a source of numbers to lbe used in computations, a precessing storage unit wherein a number is precessed one digit space per cycle, an adder-substracter wherein the nine multiples of a multiplicand or divisor are formed by adding the same to itself and its sum lon nine successive cycles, a multichannel storage unitwherein the multiples are stored, means for transmitting a multiplier to the precessing unit, a selector circuit for selecting the channels of `the multiples storage unit appropriate to a .multiplier digit on each of a plurality of successive cycles, means for applying the multiples in selected channels to the fadder-subtracter on successive cycles for addition to one ranother to form a product, means for shifting the rst multiple applied to the adder-subtracter after such application `and the sums of it and other multiples one digit space per cycle to align the same for appropriate addition to the next multiple to be transmitted to the adder-subtracter, means for transmitting the product formed in lthe adder-subtractor to the number source, means -for transmitting a dividend from the number source to the adder-subtracter, circuit means for comparing a predetermined portion -of the dividend with the nine multiples of the divisor, said comparison means controlling said selection circuit in accordance with the highest multiple divisible into the dividend to effect transmittal of said multiple to the adder-subtracter for subtraction of the same `from the dividend, means for shifting the remainder effectively one digit yspace Ifor comparison with the nine multiples, means for recording in the precessing unit the quotient digits `appropriate to the results of the comparison, and means for transmit-ting yan assembled quotient to said number source.

Other objects and `features of the invention will become apparent in -the following description when read inthe light of the drawings of which:

Fig. 1 is a general block diagram of the means of the invention;

Fig. 2 is a yblock diagram of that portion of the means of the invention which is concerned with forming the multiples of a multipli-cand yor divisor;

Fig. 3 is `a block diagram of that portion of the means of the invention which is concerned with multiplication;

Fig. 4 is a block diagram of that portion of the means of the invention which is concerned with division;

Fig. 5 is a schematic wiring diagram which illustrates the timing control means of the computer in which the means of the invention is embodied;

Fig. 6 is a schematic wiring -diagram of a precessing vstorage unit `and the controls therefor, the same being shown in Fig. 1 :in block form;

Fig. 7 is a schematic wiring diagram of the circuitry for recording the several multiples of a multiplicand or divisor;

Fig. 8 is a pulse chart which illustrates the timing of the computer in which the means lof lthe invention are embodied;

Figs. 9 and 10, taken together, are schematic wiring diagrams `of Ithe comparison circuit, the quotient control circuit, 4the quotient serial converter circuit, the multiples playback control circuit and the multiples playback selection circuit, all as shown in `block form in Fig. 1;

Fig. 11 is a `detailed lwiring diagram of a pentode coincidence gate utilizing the means of the invention;

Fig. l2 is a detailed wiring diagram of a plate connected type coincidence gate used in 'the means of the invention; y

Fig. 13 is a detailed Wiring diagram of a cathode follower type `OR gate'used in the means of the invention;

Fig. 14 is a detailed wiring diagram of -a ibi-sta'ble ilipilop fwith pullers lfor setting and resetting the same, all as used in the means ofthe invention;

Fig. l5 is a detailed wiring diagram -of a triode inverter as used Iin `the means of the invention;

KFig. `16 is Ia ow chart which illustrates the manner in which orders lcontrol the operation of the computer; and,

Fig. 17 illustrates a sample problem of division as performed by the means of the invention.

Before entering into a detailed description of the means of the invention, it is deemed desirable, first, to describe certain circuit elements which are connected together in various combinations to make up the said means.

Referring to Fig. 15, there is illustrated an electronic inverter which in the other figures is represented by an encircled 1. As shown, the inverter consists of a triode 100 of suitable type having its cathode grounded and its anode applied to the juncture of the two positivemost sections of a three-section voltage divider 101. Said voltage divider is connected across sources of +100 and -100 volt potentials and has an output line 102 projected from the center tap thereof. Utilizing the resistor values indicatedv in the drawings, the application of a volt potential to the grid of the .t1-iode to eifect conduction of the. latter causes output line 102 to assume a potential of approximately volts. Application of a -20 volt potential to the grid of the triode, however, cuts oi .the latter and the potential of output line 102 rises to approximately O volts. In the present embodiment of the invention, potentials of 0 volts and -20 volts are used throughout and, for convenience, will hereinafter be referred to asfhigh and. low respectively.

Referring now to Fig. 13, there is disclosed an. OR gate which in the other figures is represented by an encircled V. As shown, the OR gate'consists of a pair of triodes 103 having their cathodes commonly connected through a resistor 104 to a source of negative potential, say -20 volts. An output line 10S is projected fromv theV connected cathodes. Application of a low potential (-20 volts) to the grids of both triodes maintains both in cutoff condition and output line 105 assumes a potential of approximately 20 volts. However, if a high potential (0 volts) is applied to the grid :i

of either triode, the potential of output line 105 is raised by cathode follower action to approximately 0 volts. Obviously, several triodes may be connected with a common resistor 104 and output line 105.

Referring to Fig. 11, there is illustrated acoincidence gate which in the other gures is represented by an encircled G. As shown, the coincidence gate consists of a pentode of suitable type having its anode connected to a three-section voltage divider 106 of the sort described above, and its cathode connected to ground. As before, an output line 107 is projected from the center tap of the voltage divider. The screen grid of the pentode is con* nectedto a source of positive potential in the normal manner. The control and suppressor grids of the pentode, however, are connected to signal sources which assume the high and low potential levels of 0 and -20 volts. The simultaneous application of high potentials to both grids of the pentode elfects conduction thereof and output line 107 assumes a low potential (-20 volts). Application. of a low potential to either or both grids ofthe pentode etects cutott of the latter and output line 107 assumes a high potential (O volts)` Referring now to Fig. l2, there is illustrated a plate connected typev gate which in the other gures is represented by an encircled Gir As shown, a pair` of triodes Y have their anodes appliedv to a single voltage divider 110 which is provided with an output line 111 in the usual manner. A high output is produced on line 111 only when lovs7 potentials are simultaneously applied to the grids of both triodes. A low output is produced on line 111 when a high potential is applied to either or both triodes.

Referring now to Fig; 14, there is illustrated a bi-stable flip-flop which in the other gures is represented by a pair of circles and the letters FF and which will hereinafter be referred to as a tiip-tiop. As shown, the liipflop consists merely of two inverters 112 of the type shown in Fig. l5, with the output 113 of each applied to the grid of the other. Input lines 114 are` provided to the grids of puller tubes 115, plate to plate connected each with one ofthe ilip-op triodes. Puller triodes 115 are illustrated in Fig. 14 to indicate the connection thereof with the flip-flop, but it is to be understood that the lowers the potential at its anode and, therefore, the potentialof the output line ofthe non-conducting flipilop tube, to the point Where the conducting flip-flop tube is cut oi, and the conductive states of the tubes reverse. Application of a low potential (-20 volts) to one of the input lines 114 is ineective in so `far as changing the state of the dip-dop is concerned.l

It is to be understood, of course, that the circuits described above are merely by way of example and are readily replaceable by other circuits which accomplish the same results.

It is thought that in certain instances wherein compound gating circuits are made up of straightforward combinations of the basic circuits described above, the use of a single symbol which accurately depicts the makeup and function of the entire circuit will greatly facilitate an understanding of the invention.v For example, a circuit which is to pass a signal A only at B time of cycle C ofa division or multiplication operation, may include a pentode coincidence gate to which signal A and time signal B are applied, an OR gate to which signals and p. indicative of division and multiplication operations are applied, an inverter to which the output of said coincidence gate is applied, a second coincidence gate to which the outputs of the OR gate and the inverter are applied, and a second inverter controlled by the output of the second coincidence gate to produce a high signal equivalent to the signal A applied to the circuit. This arrangement or any other combination of the described basic circuits having the same result may be conveniently depicted by an appropriately labeled coincidence gate symbol' as follows:

Symbols ditering from the foregoing only in the descriptive legends applied to the inputsl thereof, are used in the drawings for the purpose aforesaid.

The computer in general "the means of the invention, although not limited to use in any particular computer, are disclosed as embodied in a computer to which they are especially well adapted. This computer is serial in form of operation and utilizes the coded decimal (l, 2, 4, 8) system of notation. A keyboard 120. (Fig. l) or another input de vice serves to enter numbers; and orders, a digit at a time, into intermediate storage units 121 and 122 respectively wherein the several digits of each number and order arev assembled in proper order for transfer to a selected location in al' general storage device 123.

The general storage device is a multichannel magnetic storagedrum of the sort disclosedin the patent to Cohen et al. #2,540,654, and consists of a rotating cylindrical member having a` homogeneous magnetic coating on its circumferential surface. The magnetic' surface of the drum is divided into. a series of contiguous peripheral channels each having recording and playback means associated therewith. The rotational speed of the drum being constant, each rotation of the drum consumes a definite number of equal time periods, in the present instance, one hundred eighty, during. each of which an area or cell of each; channel is positioned adjacent the recording means to bemagnetized thereby. As disclosed in the Cohen patent, a cell or area is magnetized with one polarity to indicate binary one and with the opposite polarity to indicate, binary zero.

In order to synchronize the recording and playback means for the several' drum channels with the rotation of the drum and'for other reasons to become apparent hereinafter, one channel of the drum, that designated a in Fig. 5, is provided with a fullcomplement on one hundred eighty magnetized spots. A second channel of the drum, that designated b, is provided with a single magnetizedV -each rotation of the drum.

Drum channel a has associated therewith a reading head which drives a pulse generator 124 adapted to produce pulse trains C, R, A and G as shown in the pulse diagram of Fig. 8. Drum channel b is provided with a reading head which drives a pulse generator 125 adapted to produce the pulse train ZD of Fig, 8. It is to be noted that the pulse trains produced by pulse generator 124 have a frequency of 180 per revolution of the drum, whereas the ZD pulses from pulse generator 125 have a frequency of one per drum revolution.

In order to facilitate the further description of the means of the invention, it will be assumed that each C pulse from generator 124 initiates a time period which terminates on the occurrence of the next following C pulse. There are, of course, 180 such time periods and they are numbered zo, t1, i179. As will appear herein after, however, time period i179 is sometimes referred to as time period t255.

Pulse generators 124 and 125 may be of any suitable sort adapted to produce the type of pulses indicated in Fig. 8. For example, pulse generator 124 may include means for developing the R pulses and multivibrators or the like for developing the delayed pulses C and A, and also inversion means to form the G pulses which, it will be noted, span the C and A pulses.

The principal purpose of the pulse train C is to advance a time period binary counter 126 one step for each pulse. This counter may be of any ordinary sort. ln the present instance, counter 126 is advanced by negative pulses. Therefore, the positive C pulses from generator 124 are applied to an inverter 127 whose output is delivered to the counter through an OR gate 128. Inasmuch as counter 126 is advanced one step by each C pulse, the state thereof at any particular time is an accurate indication of what time period of drum revolution the computer has reached. Therefore, output lines from the several stages of the counter are applied to a matrix 130 whose outputs 131 are usable for timing purposes. Matrix 130 preferably is constructed of diodes and includes among its output lines 131 one that assumes a high potential during each time period or group of time periods that is pertinent to the timing control of the computer. Matrices of this sort are well known and need not be discussedlfurther.

. In order for binary counter 126 to count through 180 steps (-179) during each of selected revolutions of drum 123, the same must include eight stages which ordinarily would enable the counter to count through 256 steps, that is, from O to 255. Means are provided, therefore, either to stop the counter when it reaches a count of 179 during the last time period of each cycle, or to skip the counter to capacity (255) at such time. operation is utilized whenever the next rotation of the drum is not to be utilized by the computer, as, for example, on the last cycle of each calculation; and the latter mode of operation is utilized whenever the next rotation of the drum is to be utilized for a cycle of operation. Obviously, it' counter 126 is skipped to count 255 at the beginning of what would otherwise be time period tm, the output of matrix 136 will not indicate -time period tm but rather will indicate time period t255. I

rlhe means whereby counter 126 is stopped at 179 includes an output line 132 of matrix 130 which is high only when said counter stands at 179 and which is applied to OR gate 12S and maintains the output of the latter high continuously. Obviously, the inverted C pulses from pulse generator 124 are ineffective to advance the counter when this condition exists, and matrix 130 continues to indicate time period tm even though drum 123 does not stop rotating.

The means whereby counter 126 is skipped to capacity (255) are under control of the A, C, G and ZD pulses from pulse generators 124 and 125 and, also, under con'- trol o f a calculating key 134 whose purpose it is to over- The former mode of` 6 come the eli'ect of stopping the counter at 179. The said means include, among other things, a binary cycle counter 136 which is advanced one step for each revolu tion of drum 123 during a calculation operation, and also one step for each digit transmitted to the computer from the keyboard during keyboard operations.

An OR gate 138 whose output, when low, advances counter 136 is under the joint control of a Go circuit flip-op 140 and a timing control circuit that includes a flip-nop 141. Go ilip-liop 140 is set to apply a low potential to gate 138 under control of Calculate key 134 and, as will presently appear, is no t reset during calculating operations until a stop signal which signifies the end of the calculation is provided. Key 134 normally connects a source of negative potential, say -20 volts, to a dilierentiator circuit 142 of which the resistor is connected to a source of positive potential. The output of the diterentiator is applied to the grid of an inverter 144 which controls a puller 146 for Go Hip-flop 140. When the Calculate key is operated, it connects a source of ground potential to the diiferentiator and a positive pulse is applied to inverter 144, but to no avail as the positive potential applied to the resistor of the diferentiator circuit normally maintains the inverter conductive. However, when the key 134 is restored to normal, a negative pulse is applied to inverter 144 to cut olf the same momentarily, and puller 146 sets flip-op 140 which applies a low potential to OR gate 138. The other input of OR gate 13Sstems from a coincidence gate 150 to which the output of flip-flop 141 and also the C pulses from pulse generator124 are applied. Flip-flop 141 is set to apply a high potential to gate 150 by a coincidence gate puller i 152 which, of course, utilizes the voltage divider of the lip-tiop triode to which it is connected. The ZD pulses from generator 12S and the G pulses from generator 124 are applied to gate 152 to effect conduction of the same and, therefore, setting ofiiip-iiop 141 during time period tm of each cycle, this being the only time at which the ZD and G pulse lines assume high potentials coincidentally, see Fig. 8. Flip-flop 141, having been set during time period im, applies a high potential to gate 150 during the remainder of said time period and into the beginning of the next following timev period when the occurrence of a C pulse eifects conduction of said gate and, therefore, the application of a low potential to OR gate 138. Remembering that ip-flop 140 has also been set to apply a low potential to OR gate 138, the latter produces a low output which advances cycle counter 136 one step.

In order to reset timing hip-flop 141 prior to the next succeeding C pulse, a reset puller 154 is connected thereto and is controlled by the A pulses from pulse generator 124. It will be noticed that the A pulse immediately follows the C pulse during each time period, so that flip-flop 141 is reset immediately following the C pulse which effects conduction of gate 150 to advance counter 136. The output of OR gate 138 is also applied through an inverter 156 to the several stages of time `period counter 126 to skip the latter to capacity (255)y each time cycle counter 136 is advanced. It is to be noted that the advance of cycle counter 136 and skipping of time period counter 126 to capacity are effected by the C pulse which occurs at the beginning of the last time period of a drum revolution, which pulse is the one that otherwise would advance the time period counter to 179. Therefore, a time period tm occurs only when the cycle counter is not advanced to initiate a cycle of operation on the next revolution of drum 123 (Fig. 8). When a time period tm does occur, however, it lasts for an indefinite period of time until the C pulse occurring during the last time period of a succeeding rotation of the drum is elective to advance the cycle counter and to skip the time period counter to capacity, see Fig. 8.

The Go tlip-op 140 is reset at appropriate times to prohibit further advance of cycle counter 136 and to prevent skipping of time pen'od counter 126 to capacity. v'lvieans to this end include la coincidence gate 158 to whichv an output of cycle counter 136, that is high on cycle one, is applied along ywith a stop signal from any suitable source such as .an operation control unit 160 (Fig. 1) controlled .by orders entered into the computer. The output of gate 158 is applied to an inverter 162 which, when the gate becomes conductive, applies a high output to a coincidence gate 161. Also applied to gate `1,61 is a signal line from one of the outputs 13-1 ,of matrix 130 that is high during time period im. Therefore, if on cycle one a stop signal is applied to gate 158, then during 'time period i140 flip-flop 140 is reset and applies a high potential to OR gate 13S. This Ihigh potential is passed on to the inputpof cycle counter 13.6 to prevent advance thereof and to the inverter 156 which controls skipping of time period counter 126 to ycapacity to prevent .such skipping.

Also applied to the grid of inverter 162 is a signal line 159 which assumes a low potential on each cycle of keyboard operation on which a digit is transmitted to the computer. The means controlling the line 159 may be of any suitable sort, such for example, as those shown in the-aforecited application Serial No. 270,876. For present purposes it is sufficient to understand that line 159, by elfecting resetting of Go iiip-op 140, limits the ad- -vance of cycle counter 136 to one step, and permits counter 126 to skip to capacity only once for each digit entered ythrough the keyboard. As will presently appear, multiplication and division operations with the means of the invention each consume 36 cycles of drum 123. Evidently counter 136 must be able to count to 36 which if, as here, said counter is binary in form, requires that the same have a capacity of 64 (2G). Therefore, means `are vprovided `to reset counter 136 to its initial one count each time it has reached the count of 36. An output line 166 of said counter, which is high when the -same stands at 36, is applied through an inverter to a plate connected type coincidence gate 168 whose output, in turn, is rapplied to the grid of a cathode follower l169 whose purpose it is to reset the cycle counter to its initial one count. The cathode follower may be substantially identical with either half of the, OR gate described hereinabove. The other input of gate 168 is taken from Lgate 150 which, it will be lremembered,

conducts only at C pulse -time of the last time period ofpeach cycle of drum 123. The effect of this connection, which in the pulse chart of Fig. 8 is represented by the line Z', is to reset cycle counter 136 at exactly the same time of cycle as the same would be advanced under the circumstances described earlier.

jln view of all of the above, it will be seen that there is valways lavailable to Vthe computer the several pulse trains described, Iandalso reference pulses indicative of `the cycle and the time period on which the computer is currently standing.

Referring now to Figs. l and 6, the intermedlate storage device, whereby information, entered into the computer from .keyboard 120 with random timing, is syn-v chronized with the computer for delivery to the general storage drum 123, will now be described briefly. First, however, it isto be mentioned that the numbers handled Avby the computer, in the present instance, contain digits, '10.on..either side of a decimal point, and that the orders orfinstructions each contain l() digits, 2 digits for address A,2 for address 2B, 2 for the operation to be performed, 2 for the address C in which the result of said operation .istoibc stored and 2 for the address D of the next order. Itis also'to be mentioned that when entering numbers into the computerthrough the keyboard, `counter 136 is utilized for counting digits rather .than cycles, that is, it countsonly those cycles during which a digit is delivered to 'the computer and never advances lbeyond 11 except on depression of atsuitable hey which controls the transferofa-number or'an order -fromrthe intermediate storage device to the general storage drum, at which time the counter advances to 12. The use of 20 digit numbers does not violate this rule .because the cycle counter is reset by appropriate decimal locating means between the Ventries of the 10th and the 11th digits of a number, all as described in the aforo-cited copending application Ser. No. 270,876.

The intermediate number storage unit 121 is shown in Fig. l as a block with the legend D92 therein. This D92 indicates a delay of 92 time periods between the delivery of information to the unit and the exit of the same information therefrom. In like manner, the D46 associated with .intermediate ,orders storage unit 122 in the drawings .indicates a delay of 46 time periods.

Associated with the intermediate numbers storage .unit 121 is a number control unit 170 which is adapted to receive information from several sources alternatively, as will vbe described at appropriate points in the description. Information from keyboard 128 in the form 'of negative pulses during the appropriate ones of a group of four time periods, in the .present instance tss, tag, f90, and im, is relayed over .a line 172 to an `inverter -174 in `unit 170 (see also Fig. 6). The output of this inverter 174 is applied directly to a gate 176 and through an inverter 178 to a second coincidence gate 180. 'Ihe outputs of gates 176 and 180 are applied to the record circuit of intermediate storage unit 121. Also applied to the gates 176 and 18@ is vthe output of a control circuit whose purpose it is to prevent recording of Ainformation in the intermediate storage device 121 at certain times. This control circuit includes a plate connected type coincidence gate 182 to -which inverted R pulses from pulse generator 124 (Fig. S) are applied to accurately time the recording of information. Also applied to gate 182 is a signal which is high only at those times when it is `not desired .to record information. The means ,for making up this signal include a coincidence gate 179 which conducts only on cycle 35 of division operations, and a pair of .coincidence gates 131 and 183 Whose plates are connected to gate 182 through a common voltage divider. Gate 181 conducts only on keyboard operations except during time period 1179 of each cycle and during all of cycle 12. Gate 183 conducts only when the computer is not on keyboard operations and the gate 179 .is cut off. Evidently .recording can Abe effected only when one of the gates 181 or 183 conducts. Other means may be provided to care .for otherfconditions if required.

In the present instance, storage unit 121includes a magnetic disc which may beon the shaft of drum 123 and is, in effect, a channel of said drum. Associated with the said disc is a record circuit 184which is driven by the coincidence gates -176 and 180, and .which may be of any known construction. Also associated with the .disc is a playback circuit 186 which includes an ampliiier `section anda flip-dop memory section vthat is set fand reset at A pulse time of each cycle in accordance with the amplitied information. Said flip-flop section includes a flip-flop 185, a pair of coincidence gate pullers 187 which are jointly controlled by the A pulses and the amplifier section, and an inverter to `apply the output of the ampliiier section to one of the gates in inverted form. Referring to Fig. 8, the output wave PB of the amplifier section includes, for each spot recorded on the disc, a positively directed lobe and a negatively directed lobe whose order of occurrence indicates the polarity of the magnetized spot. As shown, the peak of the latter lobe of each siganl wave ycoincides with an A pulse and effects appropriate setting or resetting of the flip-op 18S which indicates throughout the remainder of thetime period of 4said A pulse and until the occurrence of the A pulse during the next following time period, the value of the played back signal as binary one or binary zero. v

1t will -be noted from -the above that recordings made at R pulse time,.which is the nal portion of each time 9 period, are played back to the dip-dop 185 at A pulse time, which occurs early in each time period. In practice, the generator 124 (Fig. 5) which produces the A pulses is adjusted so that the latter occur coincidently with the peaks of the later lobes of the signal waves after the time relation of said peaks to the R pulses has been determined. The pole pieces associated with record circuit 184 and playback circuit 186 are so disposed relative to one another and the periphery of disc 183A that a delay of 92 time periods is effected between the recording of -a spot and the appearance of a signal indicative thereof at the output of the playback circuit.

The output of playback circuit 186, besides leading to the general storage drum 123, is coupled back over a line 188 to a coincidence gate 190 in the numbers control unit whoseoutput is connected to the inverter 178 and the coincidence gate 176. The second input of gate 190 is an output of an inverter 192 which is controlled from cycle counter 136 (Fig. 5) in such manner as to conduct only on cycle one, at which time it is not desired to feed information back from playback circuit 186 to the record circuit 184.

Obviously, information recorded on disc 183A during time periods tss-tgl of one cycle is played back and rerecorded during time periods to-ta of the next cycle, and again during time periods tgz-@ of the said next cycle. In order that only this four time period precession is obtained between successive deliveries of digit representative pulses from the keyboard, the latter effects application of a high potential to gate 182 on all cycles of keyboard operation except those on which a digit actually is being delivered to the computer. Means to this end are described in the copending application Serial No. 270,876 to William Burkhart et al. Obviously, therefore, each digit, after it is recorded, is precessed to make room for the next digit. After all twenty digits of a number have been recorded, they are transmitted to a selected channel of the general storage drum during time periods -tqg ofthe appropriate cycle, namely cycle 12. Referring to Fig. l, the output of playback circuit 186 (Fig. 6) of intermediate storage device 121 is applied over a line 191 to a coincidence gate 199 which is opened during time periods t0 to t7, of cycle 12 of keyboard number entry operations. Conveniently, keyboard 120 may have an output line 193 which assumes a high potential only during number entry operations and another 195 which assumes a high potential only during orders entry operations. Gate 199 is also opened at other times as will be explained hereinafter. The output of gate 199 is applied to a record circuit 194 which is common to the several channels of drum 123, and which is connected to the selected one of said channels by a selection circuit 196 which may be a relay pyramid of standard design. Operations of said pyramid to select desired channels are under the influence of a control circuit` 197 which is controlled by a selector switch on the keyboard and by orders fed into the machine, in the manner set forth in the copending application to Joseph McCarroll et al. Serial No. 255,712. Pyramid 196 also operates to connect a selected channel with a playback circuit which is here shown in two sections, the rst, labeled 198, being the record ampliers and the second section, labeled 200, being the iiipop memory portion of the circuit.

v The intermediate orders storage device 122 is substantially identical to that just above described, except that the effective delay amounts to only 46 time periods. It will be noted that this arrangement also represents a four time period precession between the recording of one orders digit and the recording of the next following orders digit. For example, an orders digit transmitted from the keyboard for recording during time periods t., to t, is rcleCOl'ded during time periods 50-53, 9699 and tug-H45 0f the same cycle and again during time periods ta-tn of the next cycle. The output of the intermediate order storage device-is applied to an operation control unit 160 which,

` 10 by -suitable gating during calculating operations, accepts only that portion of each order which refers to machine operation, and which includes means, say flip-flops, for generating a continuous indication of the operation to be performed. For example, said unit is here shown as having three outputs, one marked M for multiplication, one

marked D for division and the other marked Stop. Heref inafter, it will be assumed that these three output lines have high potentials applied thereto selectively for controlling the machine operations peculiar to each. The output of said magnetic intermediate orders storage is also applied over a line 202 and through a gate 203 to control circuit 197 to effect suitable control of the selection pyramid 196. Gate 203 is opened during time periods to-tq of cycles 1, 3, 13 and 35 of lcalculating operations to pass at each opening the address portion of the order then being transmitted from the intermediate orders storage device. Line 202 is also connected to a coincidence gate 206 whose output is applied to the record circuit 194 and which is opened to permit passage of signals during time periods t96-t135 of cycle 12 of keyboard operations on orders, this being the time that orders assembledin the intermediate storage device are transferred to the general storage drum.

Recording of orders in intermediate storage unit 122 is controlled by orders control unit 173 which may be arranged in the same manner as numbers control unit 170 to permit .recording and precessing of orders only during appropriate cycles. Referring to the orders timing chart of Fig. 16, it will be seen that on multiplication and division operations, it is desired to precess orders on all cycles save cycles 5 to 12 and 15 to 34. The reasons for this will become apparent hereinafter. The internal construction of orders control circuit 173 will not be described as it is deemed sucient for an understanding p of the invention to indicate the results obtained thereby,

particularly since the similar numbers control circuit is illustrated and described.

It will be seen, therefore, that the means thus far described are operable to enter numbers and orders into the computer digit by digit to assemble the whole numbers and orders and to shift said assemblages to selected channels in the general storage drum, wherein each number is recorded during time periods t0-79 and each order is recorded during time periods tgS-tla. The playback means 198 and record means 194 for the general storage drum utilize but a single pole piecey for each drum channel, which results in that each number is available for use by the compu-ter during time periods z1-t80 and each order is available during time periods fsw-i136, it being remembered that the flip-flop memory 200 for playback amplifier 198 is set or reset at A pulse `time of each time period in accordance with the polarity of the magnetic spot which began controlling the amplifier at the end of the preceding time period.

APrior to an operation of the computer, the control un-it 197 for general storage selector circuit 196 is set up manually in the manner described in the afore-cited t'McCarroll application 4to permit playing back of an order from a selected -channel of the drum. This order is played back yduring time periods t97-t135 of cycle 2 of the computer operation as indicated in the orders timing diagram of Fig. 16, cycle 1v being the stopped condition of the computer. The output of playback unit 198, 200 is .applied to a coincidence gate 210 which, as shownin 'Fig. 1, is opened during time periods IS7-i136 of cycle 2. The loutput of gate 210 is applied t-o a one time period delay circuit 211 which may be of'ordinary Hip-flop construction, and whose output is applied to one input terminal 212 of an adder-subtracter 213 (Figs. l and 2). Preferably, iadder-subtractor 213 is the one shown in the copending application -Sen'al No. 226,700 to William Burkhart although, if desired, `other adder-subtracters can be utilized. For present, purposes, it is sucient to understand that informationis advanced through the 11 .adder-subtracter by .the A pulses and that Athe adder-sub- .tracter i213 produce anoutput `signal indicativeof the .digital sum or difference of two digital signals applied, .one toinput terminal 21-2.and Athe other to an input terminal 214. Therefore, thesame Will not be redescribed herein. As described in theaforementioned application Serial No. 226,700, adder-.subtracter 213 is, in eifect, a .three .time period delay so that the order applied to terminal 212 thereof during .time periodstsB-rm of cycle 2 appears on vthe output line 215 of the added-subtracter .during `time `periods rmi-i140, see Fig. 16. Output line 215 is applied .through a one-time'period delay circuit v 216 to an input .of the orders control unit 173. Therefore, the said order is .recorded in the intermediate orders lstorage device during time periods fm2-i141 of cycle 2, as indicated .on the orders timing diagram. The order thus recorded in the intermediate storage device is pre- .cessed as described above so that on cycle 3 the two last recorded .digits thereof are played .back during time periods fly-t7, and .signals indicative thereof are transmitted .over line 202 .and through gate 263 to the control .unit 197 `for .the channel selection circuit 196. This4 signal sets .up .the selection circuit in such manner as to effect playback of the first number A to be .utilized in a calculation. not .again open to permit .passage of a bi-digit signal until cycle 13. During time periods :I4-tm of .cycle 3, the two 'digits `of the order pertaining to .the operation to be .performed are played back from storage ,device 122 and signals indicative thereof are transmitted .to operation control unit 160 through a .coincidence gate 220 which is open at said time. Therefore, operation control .unit v160 isset Aup to indicate on an output line thereof the operation Vto be performed .by .the .computer on the number A and ya second number B which 4is `to be obtained from the drum during a later cycle.

Selection circuit 19,6 having been set up during cycle 3, number A is played back from the drum and is applied to a coincidence gate 222 during time periods tl-tao of cycle 4. Gate 222 is opened during time periods tytso ,of cycles v.4 to -12 of multiplication or division oper- .ations and, therefore, permits repeated passage of .the pulse train indicative of number A. The output of gate 222 is applied to terminal 214 of adder-subtracter 213.

At this point it is deemed desir-able to point out that lthe number A in a multiplication operation is the multiplicand and in .a division operation .is the divisor. Therefore, inY accordance with the method of performing multi- :plication yand division utilized iby the means of the invention, it is desired to form the nine .multiples of the .numyber A whether the operation .be multiplication or division.

It 4is to be noted that gate 203 does :in the interest of clarity, .it ,is deemed desirable .to .dep scribe the means for forming the nine multiples .of the number A before determining whether itis a multiplicand or a divisor, and before describing any of the means `for co-action -thereof with a multiplier or a dividend.

As described above, the .output of adder-subtractor 213 is applied to a one time period delay circuit 216 (Figs. l and 2). The output of this delay circuit, .besides being connected to the numbers and orders control circuits land 173, is also applied to a 135 .time vperiod .delay circuit 226. This -output is, in turn, :applied to a 40 time period delay .circuit 228. Delay circuits 226 and 22S may be of any suitable sort, but preferably they `constitute magnetic discs of .the sort ldescribed in connection with intermediate storage device 121, no precessing means being provided, ofcourse. The outputof delay circuit 228 is applied to va coincidence gate 230 which is opened on cycles 15 to 12 of Amultiplication and division operations. '1" he output of gate 23.0 is .applied to the ,delay circuit .211 .whose output, it will be remembered, is connected .to terminal -212 of adder-.subtracter 213. lt is .to be noted that the combined Ydelays of .adder-sub- -tractel :D3 and delay circuits 216, 226, 228 and 211 Aamount to timeperi'ods Therefore, .the number A .applied `to terminal 214 of adder-subtracter 213 during time periods'tl-tso of cycle 4 is reapplied to the addedsubtracter 'through terminal 212 dur-ing time periods tl-tg of cycle 5. Further, -it will be remembered that gate V222 through which the number A is played back from lgeneral `storage is opened not only at the appropriate times during cycle 4, but also during cycles 5 to 12. Therefore, at the same time that lthe number is being applied to terminal 212 of the adder-subtracter after having traversed what will vhereinafter be referred-to as the `D180 loop (Figs. l and 2), the same is also being applied to Iterminal 214 of the adder-subtracter. On cycle 5, therefore, there is'produced on output line 215 of the adder-subtracter the -sum of the number A added to itself. This sum also traverses the D180 loop and has the number A added to it during cycle 6, etc. until all nine multiples of the number A are formed. The D180 loop has a branch 232 which does not include the one time period vdelay/.circuit .211 and which is applied to a multiples storage record conti-ol unit 234 whose purpose it is `to effect operation of .the appropriate one of nine record circuits 235 in accordance with each multiple transmitted thereto. Before describing the multiple storage record control .-unit, it is 'to be noted that the several multiples are applied thereto during time periods to to 1.*79 or tu of successive cycles S to 1,3. The reason for increasing the number of time periods involved from S0 to 84 is, of course, due to the fact that the multiples of number A may include one additional higher order digit.

Multiple storage record control unit 234 is illustrated in Fig. 7 and includes a pair of triodes 236 and 238 to the former of which the line 232 is applied and to the latter of which the signals on ,said line are applied through an inverter 240. The triode 236 forms with triodes 242 and 2.44 a three-way plate connected type coincidence gate. Triode 242 has applied thereto an inversion of the R pulse train from generator 124. Evidently, this inverter is cut off only at R pulse time which results in that the output of the gate of which it is a part can be high only at R pulse time. The third inverter 244 of the gate has the output of a ilip-op 246 applied thereto. Flip-hop 246 is set to apply a low potential to the tn'ode at time period tu by a puller tube 248 and is reset to apply a high potential to the inverter at time period t8., of each cycle hy a puller 250. y

The'construction is such that the output of the gate 236, 242, 244. is high only when, at R pulse time of time periods to to 84, a low'potential indicative of binary zero is applied to line 232. At all other times the output of the gate is low.

Gate 238 to which the inverted. signals from line 232 are applied is combined with a pair of inverters 252 and 254 to fogm a second three-.way plate connected type coincidence gate. Inverter 252 has the inverted R pulse train applied thereto. and inverter 254 has the output of dip-liep 2.46. applied to it.

The construction of gates 25d, 252, 238 is such that the output thereof assumes a high potential only'when, at R pulse .time of time periods t0 to tu, a high potential indicative of binary one is applied to line 232.

The outputs of the gates just described are applied to a iirst pair .of coincidence gates 2561 and a second pair of coincidence gates 25,8. The gates 258 are conditioned for conduction all during multiplication and division operations and their outputs are applied through inverters 250 to a pair of cathode followers 262. The cathode followers have their outputs connected in parallel to eight Pairs, of gates 25.6.. Evidently, counting the pair of gates 25@ above described, there are nine pairs of such gates. Each pair is associated with a channel of the storage drum and is given a .subscript lf9. to denote which one of the multiples is to be, recorded in its channel. Gates 2561 are located in parallel with the gates 253 because the ones, multiple recording channel is utilizedl in addition operations. This feature forms no part of the pres- 13 ent invention, however, and need not be discussed further. All of the gates 2561 9 have their outputs applied to inverters 264 which drive recording circuits 266 adapted each to magnetize a discrete spot on the drum with either of two polarities depending on which of the inverters produces a high output. The inverters 264 and the record circuit 235 are illustrated only in connection with the ones multiple control gate 256, it not being deemed necessary to re-illustrate the same for all of the other gates 256. The record circuits may be-of any suitable sort.

As thus far described, the multiples transmitted to the multiples storage record control circuit 234 are applied to all of the gates 256 at the proper times for recording. In order that only the appropriate multiple is recorded in each channel, the gates 2561 9 are conditioned for conduction each during the appropriate cycle 5 to 13 on which the associated multiple is transmitted thereto as described above. For example, the ones multiple is applied to the multiples record control circuit during cycle 5 and gates 2561 are conditioned for conduction during that cycle, and gates 2562 are conditioned for conduction during cycle 6, etc.

The construction is -such that during time periods t-t23 of cycles 5 to 13 the nine record circuits 235 are operated successively and all of the nine multiples are recorded on drum 123.

In the present instance, the same pole pieces which are driven by the record circuits 23S are utilized to control multiples playback circuits 270 (Figs. 1 and 2). The nine playback circuits 270 may be of the same sort as described above in connection with the intermediate numbers storage device except that only oneflip-op memory section 271 is provided for all nine, and/is connected with the latter selectively as will be described hereinafter. l At this point it is to be mentioned that, if desired, the multiples may be formed by known shortcut methods; for example, multiply by two, four, or ive ,circuits may Ibe utilized to generate the multiples rapidly. Further, where, as in the present instance, the multiples are stored in laterally spaced channels or bands of the drum, the same may be stored in a plurality of channels interlaced within the same band of the drum.

During cycle 13 of multiplication and division operations, that portion of the order which relates to the number B of the operation (multiplier or dividend) is transmitted from intermediate orders storage device 122 through gate 203 to the general storage control unit 197 (Figs. 1 and 16). This unit is set up accordingly and in turn sets up the selection circuit 196 to permit playback of number B from general storage drum 123 during cycle 14. Referring to Figs. 1, 3, and 4, the played back signals areapplied to a coincidence gate 300 which is opened during time periods t1 to t8.) of cycle 14 of multiplication and division operations to pass the same. The output of gate 300 is applied to theterminal 212 of adder-subtracter 213 whose output is connected by the delay circuit 216 and a line 309 with the numbers control unit 170 to effect recording of the number B in the inter-l mediate numbers storage unit 121. Referring to Fig. 6, which illustrates the numbers control unit' 170, there is shown a coincidence gate 302 whose output is applied to the inverter 178 and to the gate 176 which, as described above, are operated selectively to eiect recording in -the intermediate numbers storage device. One input to gate 302 stems from a flip-op 304 which is setto apply a high potential to the gate by a coincidence gate puller 306 and which is reset by an inverter puller 308. Puller 306 is operated at time period t of each cycle of a multiplication operation. Puller 308 is operated at time period t85 of every cycle. The other input of gate 302 Istems from a plate connected type gate 310 to one input of which a signal indicative of cycle 14 is applied through an inverter 312. The second input of gate 310 has inverted signals indicative of the number B applied thereto overV line 309. .These signals may be obtained by utilizing anr inverter at the output of delay unit 216, or, when the delay circuit is of flip-flop construction, by utilizing that output thereof which is the inversion of the input.

1t is believed obvious, therefore, that the number B is played back from general storage during cycle 14 and if the operation is one of multiplication, the same is applied to numbersk control unit 170 during time 'periods t5 to r2., of cycle 14 and is recorded in intermediate numbers storage device 121 during said time periods of that cycle. When the operation is one of division, the played back number B is handled differently as will appear hereinafter.

As mentioned above, the number B which is played back from general storage during cycle 14 is either a multiplier or a dividend. The manner in which the number is utilized depends upon which of thetwo the number is. The mode of operation which ensues if the numberB is the multiplier and the means for carrying out the said mode of operation will be described first.

Referring now to Figs. l and 3, an inverted output (low: l, high=0) of intermediate numbers storage device 121 is applied over a line 316 to a multiples playback control unit 318 whose function it is to set up a multiples storage playback pyramid 320 and thus effect playing back of the appropriate multiple Iof the number A, that is, the multiplicand. In Fig. 6, the output 188, 191 of playback 186 which is high (0 volts) to indicate binary one is labeled l whereas output line 316 which is low `(-20 volts) to indicate binary one is labeled I. This notation is utilized in other figures of the drawing for the same purpose. v

In order to facilitate an understandingof circuits 318 and 320 (Figs. l and 3), it is deemed desirable rst to describe the manner in which the multiplier digits are transmitted to circuit 318 by intermediate numbers storage device 121. As described hereinabove, the twenty digits of the multiplier are recorded in the intermediate storage device, lowest order digit first and highest order digit last, during time periods t5 to t2., of cycle 14. Due to the precessing nature of said storage device, the said digits are re-recorded during time periods t97 to tm of the same cycle and are played back to =be recorded again during timeperiods t9 to tag of cycle 15, etc.l That digit of the multiplier which is played back during time periods t to f2s of cycle 15 is the highest order digitthereof and, as presently will appear, is the only one which affects circuit 318 during that cycle. During cycle 16 the next to the highest order digit of the multiplier is played `back during time periods r85 to f2s and effects an operation of circuit 318. This mode of operation continues until on cycle 34 the lowest order digit of the multiplier is played back during time periods tss t0 fag.

In multiples playback control circuit 31S (Fig. 9), line 316 is applied to a coincidence gate 332 which is opened during multiplication and division operations and Whose output is applied through an inverter 334 to four coincidence gate pullers 3361, 3362, 336., and 3362. The gates 3361, 3362, 3364 and 3368 are opened during time periods t85, f2s, t27 and tas respectively, so that only the digit signals transmitted from storage device 121 during those time periods are effective to control the multiples playback control circuit. The output of gate 332 assumes a'l-ow potential and the output of inverter 334 a high potential only when high signals indicative of binary zero are applied to the gate. Therefore, each gate puller 3361, 3362, 3364 or 3368 conducts only when a binary zero is transmitted from the storage device 121 during the appropriate time period 1'85, IBG, fav, or ISB. gate pullersl 336 are applied to p-ops 338 which have been preset each to a state indicative of binary one, to reset the approprriate one or ones thereof to the opposite or zero indicating state.

The value represented by each flip-liep 338 in binary.

The

ritenesse.

coded decimal notation is indicated by a subscript 1, '2, 4 or 8 applied to its reference character. The means for setting the iiipdiops to indicate binary .one comprises a coincidence gate 340 which conducts on .application thereto of an A pulse during time period x25. The A pulses, it will be remembered, are produced by generator 124 (Fig. 5) and occur near the beginning of each time period as shown in the pulse diagram of Fig. k8. The output of gate 340 is applied to an inverter 341 Whose output in turn controls four inverter pullers 342. Each puller 342 is applied to one of the hip-flops 338 to set the latter to indicate binary one.

Evidently, therefore, the dip-hops 338 are set to indicate binary one at A pulse time of time period t25, except, possibly, flip-flop 3381 in those instances wherein its gate 3351 is made conductive to reset the flip-flop at the beginning of time period n35, it :being remembered that playback circuit 186 of storage device 121 is also controlled by the A pulses. This condition is of no matter however, as gate 3361 remains conducting `for the whole of time period 25 and yassumes complete control of flip-hop 3381 after the A pulse has passed. Later, during time periods tra, tar, and t28, one lor more, of the flip-flops 3382, 3384, and 3388 may Aalso be reset to indicate binary zero, depending on the digit transmitted from storage device 121.

Flip-flops 3331, 3382, 33,84, and 3388 are provided, respectively, with output lines d, c, b and a which assume a high potential when the associated lipfiop is set to indicate biliary one, and output lines d', c', `b' and a which assume a high potential when the associated flip- Hop is reset to indicate binary zero.

The ipops 338, through their dual output lines, control the multiples storage playback pyramid 320 Whose purpose it is to connect an output line 344 of the pyramid with the multiple playback circuit ml-mg appropriate to the multiplier digit transmitted from storage device 121 and set up in iiip-ops 338.

Pyramid 329 may be of any suitable fies the logical equations sort which satiswherein the symbol E indicates if and only if, and the symbol indicates and; and wherein the alphabetic variable designations are assumed to represent high potentials (D volts). For example, the rst equation, if spelled out, reads: The ones multiple is played back from playback circuit m1 if and only if the output lines c and b and d and a of the triggers 338 are all at the high potential of Ovolts.

An extremely eicient way of combining coincidence gates to form the pyramid, however, is arrived at by combining said logical equations into one equation wherein the symbol V indicates or and the designations ml, m2, etc. represent high outputsv from the multiples playback circuits m1, m2, etc.; and by reducing this equation to one which is particularly suited to pentode coincidence gates and which is free of the redundancies found in Equation l.

Now, to put the equation in proper form for pentode coincidence gates, use is made of the logical theorem that a'/b'.a/c' is vthe equivalent of a'.bVa.c, the symbol l denoting the negation of and, that is, a'/b denotes not n' and b'. Equation 4 becomes and nally ln Equation 7 each negation of and symbol represents a pentode coincidence gate to the grids of which the variables on either side of the symbol are applied, and each and symbol represents the connection of the plates of two pentode coincidence gates to the grid of another through a common voltage divider.

The circuit described by Equation 7 is the pyramid 320 of Fig. 9 which need not be described further except to state that the same connects output line 344 thereof only with that one of the multiples playback circuits mls-m2 appropriate to thesetup of the flip-hops 3.38 and to describe an illustrative operation thereof. It is also to be mentioned that in Fig. 9 the actual connections from the ilip-ops 338 and the playback circuits fnl-m9 to the coincidence gates of the pyramid are shown only in a few illustrative instances, the remaining connections being indicated by arrows applied to the gates and appropriately labeled.

In order to illustrate the `operation of pyramid 320, it will be assumed that the flip-Hops 3381, 3382, and 338.2 have been set to their binary one indicating positions to represent a decimal'digit 7. In this case a coincidence gate 350 to which the signals from playback circuit m7 are applied is conditioned for conduction by the output c from the llip-tiop 3382 and is made conducting by positive signals emanating from the playback circuit. The output of gate 350 is combined with that of a gate 352 which is maintained cut ol by the output c' of dip-flop 3382 and each time gate 350 conducts, it cuts off a gate 354 which is primed for conduction by the output b of the dip-flop 3382. A gate 356 whose output is connected with that of gate 354 is maiutained non-conducting by the output b' of ip-op 3384. Therefore, each time gate 354 is cut oi, a gate 358 which is primed for conduction by output d of flip-flop 3381 becomes conducting. The output of gate 358 is applied to a gate 360 in common with that of a gate 362 which is maintained non-conducting by output d' of ip-op 3382. Therefore, when gate 358 becomes` conducting, it cuts oli lgate 360 which is primed for conduction by output a' of dip-flop 3382. The output of gate 360 is combined with that of a gate 364 which is maintained cut o by the output a of dip-dop 3382. Each time gate 360 is cut off, therefore, output line 344 assumes a high potential, the same as at the output of playback circuit m2.

Output line 344 of pyramid 320 is applied (Fig. 1) to the Hip-flop memory 271 which, as described above, is common to all of the multiples playback amplifiers and which at A pulse time of each time period assumes a state indicative of the signal recorded during the preceding time period of a previous cycle. The output of unit 271 is, in turn, applied to a coincidence gate 382 Which is opened during time periods 1 to 84 of cycles 16 to 36 of multiplication operations. The output of gate 382 is applied to terminal 214 of adder-subtracter 213.

In order for each multiple which is transmitted to adder-subtracter 213 under control of a multiplier digit to become a partial product which can be added to the other partial products to produce the total product of the two numbers, A and B, the same must, in effect, be multiplied by the power of ten appropriate to the denominational position of the multiplier digit, that is, units, tens, hundreds, etc. This, of course, merely involves a relative shift of one columnar position between successive multiples prior to adding the same together. In the instant computer wherein a columnar position is represented by a group of four time periods and wherein the several multiples are applied tothe adder-subtracter during the same groups of time periods of successive cycles, the relative shift in position between succeeding multiples is obtained by re-applying the rst multiple, that is, the one appropriate to the highest order multiplier digit, to the adder-subtracter as a partial product on the same cycle as, but four time periods later than, the second multiple (that appropriate to the multiplier digit of the next lower order), and by applying the sum of these two to the adder-subtracter on the same cycle as, but four time periods later than, the third multiple, etc. ln short, the sum of previous multiples is shifted one columnar position tol the left prior to the addition thereto of each succeeding multiple. 1t will be understood, of course, that if the multiples are applied to the adder-subtracter in inverse order, that is, the one appropriate to the lowest order multiplier digit first, the re-application of the rst partial product would occur four time periods earlier than the initial application of the second multiple, etc.

ln order to achieve the outlined mode of operation, use is made of a D184 loop which includes the addersubtracter, the delay units 216, 226, 228 and 211 of the D136 loop plus a four time period delay 325 (Figs. 1 and 3). The D184 loop includes a coincidence gate 326 that is open from tlm of cycle 15 of multiplication and division operations until the computer completes the operations and stands on cycle 1. Therefore, that multiple of the multiplicand which is applied to terminal 214 of the adder-subtracter during time periods t1 to tsr of cycle 16 traverses the D184 loop and is applied to adder-subtracter terminal 212 during time periods t to tss of cycle 17, to be added to the second multiple which is applied to terminal 214 during time periods t1 to is.; of that cycle. The sum of these two multiples or partial products, also traverses the D134 loop and is applied to terminal 212 of the added-subtracter during time periods t5 to tgz of cycle 18 to be added to the third multiple which is applied to terminal 214 during time periods t1 to t8., of that cycle. This mode of operation is continued until on cycle 35 the sum of the rst nineteen multiples or partial products is applied to terminal 214 of the adder-subtracter during time periods t5 t0 1,160 to be added to the multiple appropriate to the twentieth multiplier digit which is applied to terminal 212 during time periods t1 to r8.1 of that cycle. The sum of this last addition is the product of the two numbers A and B. lt will be noted that the gate 326 in the D184 loop is closed on cycle 36 so that the product does not cycle back through the adder-subtracter.

The product obtained in the manner just above described contains forty digits, twenty on either side of the decimal point. The instant computer does not make use of all forty digits of the product but rather only the center twenty, that is, ten on either side of the decimal point. Care must be taken, therefore, in entering numbers to be multiplied into the computer to ensure that their products do not include more than ten digits on either side of the decimalrpoint, except, of course, if product ldigits beyond the tenth place to the right of the decimal point are not desired or required, in which case, the dropping of such digits is not objectionable. In order to store the twenty center digits of the product for future use, the delay unit 226 of the D180 and D184 loops described above has an output line 327 which is applied to a gate 328'(Figs. 1 and 3) that is opened during timeperiods t0 to tqg of cycle 36 of multiplication operations and whose output is applied to the record circuit 194 for general storage drum 123. Remembering that delay unit 216 constitutes a one time period delay and unit 226 a one hundred thirty-tive time period delay, the product which appears at the output of the adder-subtracter during time periods t4 to tm of cycle 35 is applied to gate 328 during time periods i140 to tm of cycle 35 and to to tm of cycle 36. As gate 328 is opened only during time periods t0 to tqg of cycle 36, only the signals applied thereto at such times are passed and only the center twenty digits of the product are recorded on drum 123.

In order for the product to be stored in a selected channel of the drum, that portion of the current order assigned to address C (the channel in which the product is to be stored) is played back during time periods to to t7 of cycle 35 (Fig. 16) and is applied to control circuit 197 to set up channel selector 196 prior to the transmittal of the product to record circuit 194.

As described hereinabove, the computer is reset to cycle 1 following cycle 36. On cycle 1, that portionof the current order assigned to address D (the location of the next order) is played back during time periods t0 to t7 and control circuit 197 sets up selector 196to effect playing back from the drum 123 of the next order for the computer. From this point'on, the operation is the same as described above if it is'to be one of multiyplication, or,lif it is one of division, as presently to he described.

When the operation of the computer is one of division rather than one of multiplication, the multiples which are formed during cycles 4 to 12 are multiples of the divisor, and the number B which is played back from general storage during cycle 14 is the dividend. According to the invention, the dividend is compared with each of the nine multiples of the divisor and the highest one of said multiples divisible thereinto is subtracted therefrom. The remainder is then shifted in time to erect a multiplication by ten and all nine multiples are compared therewithetc. The means for carrying out this program are such that on each of successive cycles 15 to 34, the dividend or a remainder thereof has subtracted therefrom the appropriate one of the nine multiples of the divisor as determined during the preceding cycle, the new remainder is shifted in time to effect a multiplication by ten, and the shifted 4remainder is com-f pared with all nine multiples of the divisor to determine which one thereof will be subtracted therefrom `during the next following cycle. y

When on cycle 14 the number B, the dividend, is played back from general storage, the same is applied via gate 300 to terminal 212 of adder-subtracter 213 (Figs. 1 and 4),. Thence the number B traverses a D140 loop which includes the adder-subtracter, delay units 216,

l226 and 211, line 327 and a coincidence gate 370 which is opened to permit use of the D loop from time period i140 of cycle 14 to time period :39 of cycle 1S of division operations. Evidently, the number B which is v.applied to terminal 212 during time periods t1 to tao Vof cycle 14 is reapplied to the terminal 212 between `time period Z141 of cycle 14 and time period L10 of cycle 15. After traversing the D140 loop the dividend is delayed a t9 further three time periods by the adder-subtracter 213 and is transmitted over a line 372 to comparison circuit 374 between time periods r1.1.; of cycle 14 and time period t4, of cycle 15.

Referring to Fig. l wherein the comparison circuit 371i is illustrated, the same includes a pair of coincidence gates 376 and 378 to the former of which the information from line 372 is applied and to the latter of which the inverse of said information is applied. Here again, line 372 may include two conductors which stem from opposite outputs of a flip-flop embodied in the addersubtracter or the same may include one conductor which is applied directly to the input of gate 376 and indirectly to the input of the gate 378 through an inverter. The

outputs of' gates 376 and 373 are applied respectively to plate connected type coincidence gates 380 and 382 whose other inputs have applied thereto an inversion of the A pulses shown on the chart of Fig. 8. Evidently, the gates 380 and 332 can produce high output potentials indicative of binary one and binary zero respectively only during A pulse time of each time period, at which times, it will be remembered, the information in the adder-subtracter is being advanced from stage to stage. In order that the gates 376 and 373, and therefore the gates 380 and 382, are controlled during each A pulse bythe output of the adder-subtracter which existed just prior to the A pulse, an integrator ordelay circuit 384 is connected in the appropriate input of each of the gates 376 and 37S. The purpose ofthis arrangement will be described hereinafter.

The other input to each of the gates 376 and 373 stems from a plate connected type coincidence gate 386 to which the output of an inverter 383 and the output of a flip-flop 390 are applied. Inverter 38S is caused to conduct and, therefore, to apply a low potential to gate 386 during cycles 1S to 34 of division operations. Flip-dop 390 is set by a triode puller to apply a low potential to said gate at time period t1 of each cycle and is not reset until the beginning of time period 1335. Therefore, gate 386 is cut off and delivers a high potential to the gates 376 and 378 throughout time periods t1 to 84, of cycles to 34 of division operations. Gates 376 and 378, of course, conduct during such times only on the application thereto of the appropriate information signals. When gate 376 or gate 37S does conduct, however, it eifects cutoff of the associated gate 380 or 382 which produces a high output potential at A pulse time. The outputs of gates 380 and 382 are applied to cathode followers 392 and 394, of which the former delivers a high potential on application of each binary one to the comparison circuit whereas the latter delivers a high potential only on application to the comparison circuit of a binary zero. The outputs of cathode followers 394 and 392 are applied each to nine coincidence gates 396 or 398 respectively. means for comparing each of the nine multiples with the dividend or a remainder thereof. Before entering into a description of said means, however, it is deemed desirable iirst to discuss the principle of operation thereof as applied to division.

In order to determine each quotient digit in division, it is necessary to compare all nine multiples of the divisor with the dividend (in the case of the highest order quotient digit) or with ten times a remainder of the latter (for all other quotient digits). For example, if the fourth multiple of the divisor is less than or equal to ten times a remainder while the fifth multiple is larger than the same, then the quotient digit is four. This comparison of each of the nine multiples is accomplished i by nine comparison circuits to each of which one particular multiple is applied along with the dividend or ten times a remainder thereof. Each comparison circuit may include a flip-flop which is reset if the dividend or ten times a remainder thereof is greater than or equal The gates 396 and 398 control f fil) to the multiple and which is set otherwise. If two numbers n1 and n2 are compared digit by digit starting from the lowest order digits, the flip-flop being reset whenever a digit of n1 is greater than the corresponding digit of n2 and being set when a digit of 111 is less than the corresponding digit of n2, and on resetting or setting action being accomplished when corresponding digits of the two numbers are equal, then the state of the dip-dop following comparison of the highest order digits of the number is indicative of the relative sizes of the numbers n1 and n2. The flip-flop will be in the reset state if n1 n2 and in the set state if f12 n1. If the flip-dop is reset initially, however, and the two numbers are equal, it will remain reset so that a reset state of the flip-flop following the last comparison indicates that nlnz while the set state indicates n2 111. lt is to be noted that this method of comparison gives priority to higher order digits and may be utilized with -any system of notation wherein successive digits are given greater Weights. For example, when the binary coded decimal notation (l, 2, 4, S, l0, 20, 40, 80, etc.) is utilized, comparison is on a binary lbasis and the binary digits 1, 2, 4, 8, l0, etc. are compared successively in the order given.

Referring again to the comparison gates 396 and 398, which it will be remembered are controlled in part by the outputs of cathode followers 394 and 392 respectively, the second input to each gate 396 is the output of one of the multiples playback circuits rc1-m9, while the second input to each of the gates 398 is the inverse of that which is applied to the associated gate 396. This inversion is readily accomplished by inverter triodes located in the output lines of the multiples playback circuits Inl-m9.

Each pair of gates 396 and 398 serves as pullers for a iiip-op 402. For convenience, each gate 396 may be considered as setting its ip-flop while each gate 398 may be considered as resetting the same. In addition to the reset pullers 398, each flip-dop is also provided with a triode puller 464 which is operated at a convenient time, say time period to. lf desired, a suitably connected master puller may be provided for all of the dip-Hops. The purpose of the pullers 464 is to assure that all of the dip-flops are in their reset state preparatory to each comparison. The fiip-iiops 402 which are designated FP1, FP2, FF-g for convenience have the values l, 2, 3, 9 appropriate to the multiples which are transmitted to the gate pullers therefor, and the outputs of each are conveniently labeled K1 and K1', K2 and K2', etc.

Referring to Figs. l and 4, the nine multiples playback amplifiers mrmg are connected directly to the flipflop pullers in the comparison circuit by lines 1536, so that all nine multiples are played back. to the pullers coincidentally. It will be remembered that the multiples are recorded during time periods to-zvm of each cycle and that (Fig. 8) signal peaks indicative of a played baci; multiples digit appear at the output of the playback ainpliiiers at A pulse time of time periods trim or" each cycle. Therefore, the gate pullers 396 and 393 are conditioned for conduction selectively, in accordance with the values of the multiples, at A pulse time of each time period 1484. The dividend with which the multiples are first compared is transmitted from the Adder-subtracter to the gates 376 and 378 of the comparison circuit between time period tm of cycle 31.4 and time periti-l L13 of cycle 15 inclusive. Remembering that the signals from the Adder-subtracter commence on the occurrf-:ncc` of each A pulse and last until the next, and that the dlay circuit 384 in the input of each gate 376 and iff/tl prevents application of each said signal to the gate until the A pulse which initiates the same has passed, the gates 376 and 378 are controlled by said signals between time period i of cycle 14 and time period r4., of cycle 15 inclusive. However, the other input to each gate 376 

